Semiconductor Research: The Foundation of the AI and Robotics Era

A material with electrical conductivity between a conductor and insulator, typically silicon, whose properties can be modified by adding impurities (doping) to create transistors and integrated circuits.

The primary material used in semiconductor manufacturing due to its abundance, stable properties, and ability to form high-quality oxide layers. Silicon wafers serve as the substrate for chip fabrication.

The fundamental building block of modern electronics—a semiconductor device that can amplify or switch electrical signals. Modern chips contain billions of transistors, each acting as a microscopic on/off switch.

A complete electronic circuit fabricated on a single piece of semiconductor material, containing transistors, resistors, capacitors, and interconnections. Also called a "chip" or "microchip."

A single functional unit on a semiconductor wafer before it's packaged. After testing and packaging, a die becomes a finished chip.

A thin, circular slice of semiconductor material (typically 200mm or 300mm diameter) on which hundreds of chips are fabricated simultaneously through photolithography and etching processes.

A semiconductor fabrication plant that manufactures chips designed by other companies. TSMC and Samsung are leading foundries, producing chips for Apple, NVIDIA, AMD, and others.

An ultra-clean manufacturing facility where semiconductor wafers are processed. Modern fabs cost $10-20 billion to build and require Class 1 cleanrooms (fewer than 1 particle per cubic foot of air).

A nominal measurement indicating the manufacturing technology generation (e.g., 5nm, 3nm). Smaller nodes generally mean more transistors per chip, better performance, and lower power consumption, though the number no longer directly represents physical feature sizes.

The process of transferring circuit patterns onto silicon wafers using light (photolithography) or extreme ultraviolet radiation (EUV). Critical for creating the microscopic features of modern chips.

Advanced lithography technology using 13.5nm wavelength light to pattern features smaller than 7nm. ASML is the only company manufacturing EUV systems, which cost over $150 million each.

The process of intentionally introducing impurities (like boron or phosphorus) into pure silicon to modify its electrical properties and create n-type or p-type semiconductors.

The process of selectively removing material from a wafer to create circuit patterns, using either chemical solutions (wet etching) or plasma (dry etching).

The percentage of functional chips produced from a wafer. Higher yields reduce manufacturing costs. Typical yields range from 70-95% depending on complexity and maturity of the process.

The general-purpose processor that executes program instructions sequentially. CPUs excel at complex logic and control flow but are less efficient than specialized chips for parallel workloads like AI or graphics.

Originally designed for graphics rendering, GPUs contain thousands of smaller cores optimized for parallel processing. Now essential for AI/ML training and inference due to their ability to perform massive matrix operations simultaneously.

Google's custom-designed AI accelerator optimized specifically for neural network computations. TPUs offer superior efficiency for TensorFlow workloads compared to general-purpose GPUs.

A specialized processor designed for accelerating neural network operations, typically integrated into mobile devices and edge computing platforms for on-device AI inference.

A chip designed for a specific application rather than general-purpose computing. ASICs offer maximum efficiency for targeted workloads (e.g., Bitcoin mining, AI inference) but cannot be reprogrammed.

A reconfigurable chip that can be programmed after manufacturing to implement custom digital circuits. FPGAs offer flexibility between general CPUs and specialized ASICs, used in prototyping and specialized computing tasks.

An integrated circuit combining multiple components (CPU, GPU, memory, I/O controllers) on a single chip. Apple's M-series and smartphone processors are SoCs, offering better performance and power efficiency than discrete components.

A compact integrated circuit containing a processor, memory, and I/O peripherals, designed for embedded control applications in IoT devices, robotics, and automotive systems.

Volatile memory that temporarily stores data and program instructions while a computer is running. Faster than storage but loses contents when powered off.

The most common type of RAM, storing data as electrical charges in capacitors that must be refreshed thousands of times per second. Used for main system memory due to high density and low cost.

Faster but more expensive than DRAM, using transistor circuits that don't require refresh. Used for CPU caches due to speed advantages, despite lower density.

Advanced memory technology stacking DRAM dies vertically and connecting them with through-silicon vias. Provides massive bandwidth (up to 1TB/s) essential for high-end GPUs and AI accelerators.

Specialized high-bandwidth memory designed for graphics cards and gaming applications, offering higher data rates than standard DDR memory.

Non-volatile storage that retains data without power, used in SSDs, USB drives, and smartphones. Based on floating-gate transistors that trap electrical charge.

The most common type of flash memory, organized in pages and blocks. Used in SSDs and memory cards with different types (SLC, MLC, TLC, QLC) trading durability for capacity.

Small, extremely fast memory located close to the processor core (L1, L2, L3) that stores frequently accessed data, dramatically reducing average memory access time.

Specialized processing units in NVIDIA GPUs designed to accelerate matrix multiplication operations (tensor operations) used in deep learning. Provide 10-20x speedup for AI workloads compared to standard CUDA cores.

The fundamental parallel processing unit in NVIDIA GPUs. Modern GPUs contain thousands of CUDA cores that execute computations simultaneously, enabling massive parallelism for graphics and AI workloads.

Hardware optimized for running trained AI models (inference) rather than training them. Inference accelerators prioritize low latency and power efficiency over raw training performance.

Apple's dedicated AI processor integrated into their chips, capable of trillions of operations per second for machine learning tasks like image recognition, natural language processing, and computational photography.

Low-power processors designed to run AI models on devices (smartphones, IoT, cameras) rather than in cloud data centers, enabling real-time processing, privacy, and offline operation.

Processors inspired by biological neural networks, using event-driven computation and analog circuits to achieve extreme energy efficiency for AI tasks. Intel Loihi and IBM TrueNorth are examples.

Using different numerical precisions (FP32, FP16, INT8) for different operations to optimize performance and memory usage. AI workloads often use lower precision without significant accuracy loss.

A measure of computing performance, especially relevant for AI and scientific computing. Modern AI accelerators achieve hundreds of teraFLOPS (trillions of operations per second).

The frequency at which a processor executes instructions, measured in gigahertz (billions of cycles per second). Higher clock speeds generally mean faster processing, but power consumption increases significantly.

The rate at which data can be transferred between components (e.g., memory bandwidth, interconnect bandwidth). Measured in GB/s or TB/s, critical for data-intensive workloads like AI and graphics.

The time delay between a request and response. Low latency is critical for real-time applications like autonomous driving, gaming, and high-frequency trading.

The maximum amount of heat a chip generates under normal operation, measured in watts. Determines cooling requirements and practical deployment constraints.

The amount of work completed per unit time. In AI, often measured in images/second for inference or examples/second for training.

The number of independent processing units in a chip. More cores enable better parallel processing but don't always translate to proportional performance gains due to overhead.

A measure of processor efficiency indicating how many instructions can be executed in a single clock cycle. Architectural improvements increase IPC without raising clock speed.

High-speed interface standard connecting GPUs, SSDs, and other peripherals to the CPU. PCIe 5.0 offers 32 GT/s per lane, essential for feeding data to hungry AI accelerators.

NVIDIA's proprietary high-bandwidth interconnect enabling direct GPU-to-GPU communication at up to 900 GB/s, far exceeding PCIe bandwidth for multi-GPU AI training.

AMD's interconnect technology linking CPU cores, GPUs, and memory with high bandwidth and low latency, enabling efficient data sharing in their processors.

Industry-standard interconnect enabling CPUs to efficiently access accelerator memory and share memory pools, critical for heterogeneous computing and AI workloads.

Circuits that convert parallel data to serial for high-speed transmission and back to parallel. Essential for chip-to-chip communication at multi-gigabit rates.

A 3D transistor structure with a fin-shaped channel that allows better control of current flow. Enabled continuation of Moore's Law below 22nm by reducing power leakage.

Next-generation transistor architecture beyond FinFET, where the gate completely surrounds the channel. Samsung's 3nm and beyond use GAA for improved performance and efficiency.

Modular chip design where multiple smaller dies are combined into one package, allowing mixing of different process nodes and reducing manufacturing costs. AMD's Ryzen and EPYC use chiplet architectures.

Advanced packaging techniques stacking chips vertically or placing them side-by-side on an interposer, enabling higher density and shorter interconnects than traditional packaging.

Vertical electrical connections passing through silicon dies, enabling 3D chip stacking with high bandwidth and low latency. Critical for HBM memory and advanced packaging.

The observation that transistor density on chips doubles approximately every two years, driving exponential growth in computing power. While slowing, innovations in architecture and packaging continue progress.

The principle that as transistors shrink, power density remains constant because voltage and current scale down. Broke down around 2005, leading to multi-core processors and specialized accelerators.

Using light instead of electricity for data transmission in chips. Silicon photonics promises 100x higher bandwidth with lower power for chip-to-chip communication in future data centers.

Nanoscale semiconductor particles with unique optical and electronic properties. Potential applications in quantum computing, displays, and biological imaging.

Companies that design chips but outsource manufacturing to foundries. NVIDIA, AMD, Qualcomm, and Apple are fabless, focusing on design while TSMC/Samsung handle production.

Companies that both design and manufacture their own chips. Intel and Samsung are IDMs with in-house fabs, though Intel now offers foundry services to others.

Pre-designed circuit blocks licensed for integration into custom chips. ARM licenses processor IP that powers most smartphones and increasingly data center servers.

Software tools for designing and verifying integrated circuits. Synopsys, Cadence, and Mentor Graphics dominate this critical enabler of chip design.

The final stage of chip design when the completed design is sent to the foundry for manufacturing. Historically referred to recording the design on magnetic tape.

The complex global network of suppliers, manufacturers, and logistics spanning raw materials (silicon, rare earths) to finished chips. Concentrated in East Asia, creating geopolitical vulnerabilities.

Vulnerabilities arising from semiconductor manufacturing concentration in Taiwan and South Korea. Trade restrictions, export controls, and potential conflicts threaten global chip supply.